Post-Doctoral Researcher |
|
C6-109, UPC Campus Nord |
Abhijit Das
About
I am a Post-Doctoral Researcher in the N3Cat group of UPC BarcelonaTech, hosted by Dr. Sergi Abadal. Previously, I was a Post-Doctoral Researcher in the TARAN team of INRIA. Prior to that, I was a Senior Silicon Design Engineer at AMD, where I was part of the performance modelling team that designed the Zen microarchitecture.
I received the prestigious Best PhD Thesis Award in Computer Science & Engineering from Indian Institute of Technology (IIT) Guwahati, India, where I was supervised by Dr. John Jose. My dissertation focused on the design of data-aware on-chip networks to improve the performance of many-core systems. One of my works presented at ICCD 2020 can be found here, and an extended abstract/summary of my dissertation presented at DAC PhD Forum 2021 can be found here.
My broad area of research is Computer Architecture, and I frequently collaborate with Dr. Maurizio Palesi of University of Catania, Italy and Prof. Prabhat Mishra of University of Florida, USA. Currently, I am involved in multiple projects that focus on the design of efficient on-chip networks, caches and DNN accelerators.
I work with the gem5 simulator and have recorded multiple tutorial videos to get started with it. My videos have one of the highest number of views (29K+) on YouTube among all the gem5 simulator based tutorials. Anyone interested in learning the gem5 simulator may consider checking some of the videos here.
Research Interests
On-Chip Networks and Memory Systems
Deep Neural Network (DNN) Accelerators
Recent News
06-03-2023 : I have joined the N3Cat group of UPC BarcelonaTech
02-03-2023 : Our paper is accepted at ADOPT@IPDPS 2023
26-09-2022 : I am invited to serve as the Virtual Logistics Chair of NOCS 2022
18-08-2022 : Our paper is accepted at NoCArc@MICRO 2022
06-07-2022 : Our paper received the Best Student Paper Award at ISVLSI 2022
24-06-2022 : I am invited to serve as the Publicity Chair of NoCArc 2022
17-06-2022 : My dissertation received the Best PhD Thesis Award at IIT Guwahati
Publications
Dissertation
[PhD Thesis | PDF | DOI | Best PhD Thesis Award]
Designing Data-Aware Network-on-Chip for Performance
Abhijit Das
Indian Institute of Technology (IIT) Guwahati, Assam, India, October 2021
Book Chapter
[NoC S&P 2021 | DOI]
Trojan-Aware Network-on-Chip Routing
Manju R., Abhijit Das, John Jose and Prabhat Mishra
Network-on-Chip Security and Privacy, Springer 2021
Journal
[IEEE CEM 2022 | PDF | DOI]
Revising NoC in Future Multi-Core based Consumer Electronics for Performance
Abhijit Das, Abhishek Kumar, John Jose and Maurizio Palesi
IEEE Consumer Electronics Magazine, Vol: 11, No: 3, 2022
[IEEE TVLSI 2021 | PDF | DOI]
Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems
Abhijit Das, John Jose and Prabhat Mishra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol: 29, No: 9, 2021
[IEEE TC 2021 | PDF | DOI]
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty
Abhijit Das, Abhishek Kumar, John Jose and Maurizio Palesi
IEEE Transactions on Computers, Vol: 70, No: 6, 2021
Conferences
[ISVLSI 2022 | PDF | DOI | Best Student Paper Award]
Designing Data-Aware Network-on-Chip for Performance
Abhijit Das and John Jose
21st IEEE Computer Society Annual Symposium on VLSI, Paphos, Cyprus, July 2022
[ISVLSI 2022 | PDF | DOI]
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC
Manju R., Abhijit Das and John Jose
21st IEEE Computer Society Annual Symposium on VLSI, Paphos, Cyprus, July 2022
[ICCD 2020 | PDF | DOI | Video]
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers
Abhijit Das, Abhishek Kumar and John Jose
38th IEEE International Conference on Computer Design, Connecticut, USA, October 2020
[NOCS 2020 | PDF | DOI | Video]
SECTAR: Secure NoC using Trojan Aware Routing
Manju R., Abhijit Das, John Jose and Prabhat Mishra
14th IEEE/ACM International Symposium on Networks-on-Chip, Hamburg, Germany, September 2020
[ISVLSI 2020 | PDF | DOI | Video | Best Paper Candidate]
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-Processors
Abhijit Das, Abhishek Kumar, John Jose and Maurizio Palesi
19th IEEE Computer Society Annual Symposium on VLSI, Limassol, Cyprus, July 2020
[NOCS 2018 | PDF | DOI]
Critical Packet Prioritisation by Slack-Aware Re-routing in On-Chip Networks
Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose and Maurizio Palesi
12th IEEE/ACM International Symposium on Networks-on-Chip, Torino, Italy, October 2018
[VLSID 2018 | PDF | DOI]
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
John Jose and Abhijit Das
31st IEEE International Conference on VLSI Design, Pune, India, January 2018
[VLSI-SoC 2017 | PDF | DOI]
Implementation and Analysis of Hotspot Mitigation in Mesh NoCs by Cost-Effective Deflection Routing Technique
Reshma Raj R. S., Abhijit Das and John Jose
25th IFIP/IEEE International Conference on Very Large Scale Integration, Abu Dhabi, UAE, October 2017
[VDAT 2017 | PDF | DOI]
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs
Aswathy N. S., Reshma Raj R. S., Abhijit Das, John Jose and Josna V. R.
21st International Symposium on VLSI Design and Test, Roorkee, India, June 2017
Workshops
[ADOPT@IPDPS 2023 | PDF | DOI]
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators
Maurizio Palesi, Enrico Russo, Abhijit Das and John Jose
2nd International Workshop on AI for Datacenter Optimization at
37th IEEE International Parallel and Distributed Processing Symposium, Florida, USA, May 2023
[NoCArc@MICRO 2022 | PDF | DOI]
WiBS: A Modular and Scalable Wireless Infrastructure in a Cycle-Accurate NoC Simulator
Manjari Saha, Abhijit Das and John Jose
15th International Workshop on Network on Chip Architectures at
55th IEEE/ACM International Symposium on Microarchitecture, Chicago, USA, October 2022
Others
[arXiv 2022 | PDF | DOI]
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators
Abhijit Das, Enrico Russo and Maurizio Palesi
[DAC 2021 | PhD Forum | Video]
Designing Data-Aware Network-on-Chip for Performance
Abhijit Das
58th ACM/IEEE Design Automation Conference, San Francisco, USA, December 2021
[IRISS 2019 | ACM India Annual Event]
Critical Packet Prioritisation by Slack-Aware Re-routing in On-Chip Networks
Abhijit Das
13th Inter-Research-Institute Student Seminar in Computer Science, Kochi, India, February 2019
[VLSI-SoC 2018 | PhD Forum | 3rd Best Poster Award]
Optimising NoC in Many-Core Systems
Abhijit Das
26th IFIP/IEEE International Conference on Very Large Scale Integration, Verona, Italy, October 2018
[RC 2018 | Poster | Best Poster Award]
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
Abhijit Das, Dipika Deb and John Jose
4th Research Conclave, Indian Institute of Technology (IIT) Guwahati, Assam, India, March 2018
[VLSID 2018 | PhD Forum]
Adaptive NoC Routers for Congestion Management
Abhijit Das
31st IEEE International Conference on VLSI Design, Pune, India, January 2018