---

Post-Doctoral Researcher NaNoNetworking Center in Catalunya (N3Cat) Universitat Politècnica de Catalunya (UPC)

D6-002, UPC Campus Nord Jordi Girona 1-3, Barcelona, Catalunya, Spain - 08034 Email: abhijit.das at upc.edu

Abhijit Das

---

---

About

I am a Post-Doctoral Researcher in the N3Cat group of UPC BarcelonaTech, hosted by Dr. Sergi Abadal. Previously, I was a Post-Doctoral Researcher in the TARAN team of INRIA. Prior to that, I was a Senior Silicon Design Engineer at AMD, where I was part of the performance modelling team that designed the Zen microarchitecture.

I received the prestigious Best PhD Thesis Award in Computer Science & Engineering from Indian Institute of Technology (IIT) Guwahati, India. My dissertation explored the design of data-aware chip-scale networks to improve the performance of many-core systems. An extended abstract/summary of my dissertation presented at DAC PhD Forum 2021 can be found here.

My broad area of research is Computer Architecture and currently, I am involved in multiple projects that focus on the design of efficient chip and package-scale networks, caches and Deep Neural Network (DNN) accelerators.

I create video tutorials for using the gem5 simulator. They are among the most popular gem5 tutorials on YouTube, with over 32K+ views. If you are looking to learn using gem5, you might find these tutorials helpful. Check them out here. I built and maintain CA Deadlines, a website showing countdowns to top Computer Architecture (CA) conference deadlines.

Recent News

---

Back to Top

---