Director of Research NaNoNetworking Center in Catalunya (N3Cat) Universitat Politècnica de Catalunya (UPC)

D6-002, UPC Campus Nord Jordi Girona 1-3, Barcelona, Catalunya, Spain - 08034 Email: abhijit.das at upc.edu

Abhijit Das

About

I am a Director of Research and Group Leader at the N3Cat Centre of UPC BarcelonaTech. Before this role, I was a Post-Doctoral Researcher with the TARAN team at INRIA. Earlier in my career, I briefly worked as a Senior Silicon Design Engineer at AMD, contributing to the performance modeling team responsible for the Zen microarchitecture.

I was honored with the Best PhD Thesis Award in Computer Science & Engineering from the Indian Institute of Technology (IIT) Guwahati, India. My dissertation focused on designing data-aware chip-scale networks to enhance the performance of many-core systems. An extended abstract of my dissertation, presented at DAC PhD Forum 2021, is available here.

My research primarily revolves around Computer Architecture, with current projects aimed at developing efficient chip and package-scale networks, caches, and Deep Neural Network (DNN) accelerators.

Additionally, I produce video tutorials on using the gem5 simulator, which are among the most popular on YouTube, garnering over 32K views. If you are interested in learning gem5, you can find these tutorials here. I also created and maintain CA Deadlines, a website that provides countdowns to top Computer Architecture conference deadlines.

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